This invention relates to a method and apparatus for error correction, and more particularly to a method and apparatus for error correction suitable for use in, for example, a teletext system.
In a teletext system, a digital signal is superimposed on the horizontal scanning period in the vertical blanking period of a television signal. The conventional televison signal has no picture signal in this vertical blanking period of the horizontal scanning. The character transmission system of such a teletext system contains both a pattern transmission system in which character and picture data are dissolved into picture elements, and a coded transmission system in which the pictorial information is transmitted in the form of coded data. The coded transmission system is superior to the pattern transmission system in terms of the amount of pictorial information transmitted per unit time. The coded transmission system, however, has a problem in that a code error occuring during the transmission of data in the digital signal form is visualized as a miswritten or omitted word.
To cope with this problem, it has been proposed that the code error be corrected by improving the reliability of digital signal processing. A prior art correction system for such a purpose employs a (272,190) shortened (majority) difference set cyclic code system. This correction system is disclosed in the Report of the Radio Council (DENPA GIJUTSU SHINGIKAI) of Japan, Chapter 4, pp 171-190, and in Japanese patent disclosure (KOKAI) No. 59-133751. In this correction system, a majority difference set cyclic code of (273,191) is reduced in its required number of bits by one bit (this correction system being capable of dealing with a code error of a maximum of 8 bits), while retaining a correction capability. More specifically, a data field of 190 bits is associatively followed by an error correction field of 82 bits, which is generated by a predetermined polynomial generator. A total of 272 bits for the data field and the error correction field are thus contained in one data packet for transmission. On the receiving side, the received data packet is stored in a RAM. Then, a CPU reads out and transfers the data to a syndrome register of a predetermined number of bits (for example, 82 bits) and also to a shift register of 272 bits which acts as a delay circuit to synchronize the data with the output of corrected data.
In the syndrome register, the 272-bit data is operated upon several times. The syndrome operation is a kind of division in which, if no error is found in the data, the data is divided to provide a "0" output. The results of the syndrome operations are classified into a predetermined number of groups which are then supplied to a majority logic circuit. On the basis of the operation results, the majority logic circuit decides whether the data is to be corrected or not. The decision signal output from the majority logic circuit, together with the synchronizing output signal of the 272-bit shift register, is transferred to a correction circuit. The correction circuit, if the decision signal requires error correction, corrects the error and then writes the corrected data into the RAM.
As stated above, this correction system can correct a maximum of eight error bits in 272 bits of data, but it may fail to correct all the error bits in some cases. It is, therefore, necessary to check as to whether or not all the error bits have been corrected. This check is made in the following way.
First, the contents of the 82 registers provided in the syndrome register are checked. If the 82 bits stored in these registers are all "0's", all the error bits have been corrected. Otherwise, it is understood that all the error bits have not been corrected. Hence, the 82 bits from the syndrome register are ORed, and the CPU fetches the data showing this logical sum. The logical sum indicates correction of all the bits when its value is "0", and an incomplete correction of bits when its value is "1".
In the prior art system, the data to be corrected is outputted from the RAM to the syndrome register, and the corrected data is outputted from the syndrome register back to the RAM. The CPU performs both data transferring operations in accordance with a program designed (software) for this purpose. Therefore, the time taken for error correction depends largely on the input/output speed of the CPU. If, however, the processing time of the CPU is increased during the input/output operation, the CPU can not execute other processing, e.g., decoding processing of the received data. The CPU also often fails to follow up processing of the incoming data. Further, the prior art error correction control circuit uses the 272-bit shift register for synchronizing the output of the correction signal with the data. As a result, the error correction control circuit is large, a grave disadvantage when the error correction control circuit is fabricated into an integrated circuit.
For detecting a state of the error correction process, the outputs of the respective registers in the syndrome register are ORed. This large number, 82, of inputs requires extremely long wires, thereby adding to the overall size of the circuit and making it difficult to fabricate the error correction control circuit by means of IC technology.